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ltc6240/ltc6241/ltc6242 1 624012fe single/dual/quad 18mhz, low noise, rail-to-rail output, cmos op amps the ltc ? 6240/6241/ltc6242 are single, dual and quad low noise, low offset, rail-to-rail output, unity gain stable cmos op amps that feature 1pa of input bias current. input bias current is guaranteed to be 1pa max on the single ltc6240. the 0.1hz to 10hz noise of only 550nv p-p , along with an offset of just 125v are signi? cant improvements over traditional cmos op amps. additionally, noise is guaranteed to be less than 10nv/ hz at 1khz. an 18mhz gain bandwidth, and 10v/s slew rate, along with the wide supply range and low input capacitance, make them perfect for use as fast signal processing ampli? ers. these op amps have an output stage that swings within 30mv of either supply rail to maximize the signal dynamic range in low supply applications. the input common mode range extends to the negative supply. they are fully speci- ? ed on 3v and 5v, and an hv version guarantees operation on supplies up to 5v. the ltc6240 is available in the 8-pin so and the 5-pin sot- 23 packages. the ltc6241 is available in the 8-pin so, and for compact designs it is packaged in a tiny dual ? ne pitch leadless (dfn) package. the ltc6242 is available in the 16-pin ssop as well as the 5mm 3mm dfn package. n photo diode ampli? ers n charge coupled ampli? ers n low noise signal processing n medical instrumentation n high impedance transducer ampli? er n 0.1hz to 10hz noise: 550nv p-p n input bias current: 0.2pa (typ at 25c) 1pa max (ltc6240) n low offset voltage: 125v max n low offset drift: 2.5v/c max n gain bandwidth product: 18mhz n output swings rail-to-rail n supply operation: 2.8v to 6v ltc6240/ltc6241/ltc6242 2.8v to 5.5v ltc6240hv/ltc6241hv/ltc6242hv n low input capacitance n h-grade temperature range: C40c to 125c n single ltc6240 in 5-pin low pro? le (1mm) thinsot? package and 8-pin so for pcb guard ring n dual ltc6241 in 8-pin so and tiny dfn packages n quad ltc6242 in 16-pin ssop and 5mm 3mm dfn packages low noise single-ended input to differential output ampli? er noise voltage vs frequency l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. typical application description features applications + C r2 200k c1 10pf c2 10pf +2.5v C2.5v 6241 ta01a r4 4.99k r1 200k v in v out + v out C 1/2 ltc6241 + C 1/2 ltc6241 c3 10pf r3 4.99k c4 10pf frequency (hz) 20 10 noise voltage (nv/ hz ) 30 40 50 60 1 100 1k 100k 6241 ta01b 0 10 10k t a = 25c v s = 2.5v v cm = 0v
ltc6240/ltc6241/ltc6242 2 624012fe total supply voltage (v + to v C ) ltc6240/ltc6241/ltc6242 ...................................7v ltc6240hv/ltc6241hv/ltc6242hv .................... 12v input voltage .......................... (v + + 0.3v) to (v C C 0.3v) input current ........................................................ 10ma output short-circuit duration (note 2) ............ inde? nite operating temperature range ltc6240c/ltc6241c/ltc6242c ..........C40c to 85c ltc6240i/ltc6241i/ltc6242i .............C40c to 85c ltc6240h/ltc6241h/ltc6242h ....... C40c to 125c (note 1) speci? ed temperature range (note 3) ltc6240c/ltc6241c/ltc6242c .............. 0c to 70c ltc6240i/ltc6241i/ltc6242i .............C40c to 85c ltc6240h/ltc6241h/ltc6242h ....... C40c to 125c junction temperature ........................................... 150c dhc, dd package ............................................. 125c storage temperature range .................. C65c to 150c dhc, dd package .............................. C65c to 125c lead temperature (soldering, 10 sec)................... 300c absolute maximum ratings ltc6240 ltc6240 out 1 v C 2 top view s5 package 5-lead plastic tsot-23 +in 3 5 v + 4 Cin C + t jmax = 150c, ja = 250c/w 1 2 3 4 8 7 6 5 top view nc v + out nc nc Cin +in v C s8 package 8-lead plastic so C + t jmax = 150c, ja = 190c/w ltc6241 ltc6241 top view dd package 8-lead (3mm s 3mm) plastic dfn 5 6 7 8 4 3 2 1 out a Cin a +in a v C v + out b Cin b +in b b a t jmax = 125c, ja = 43c/w underside metal connected to v C (pcb connection optional) 1 2 3 4 8 7 6 5 top view v + out b Cin b +in b out a Cin a +in a v C s8 package 8-lead plastic so b a t jmax = 150c, ja = 190c/w ltc6242 ltc6242 16 15 14 13 12 11 10 9 17 1 2 3 4 5 6 7 8 out d Cin d +in d v C +in c Cin c out c nc out a Cin a +in a v + +in b Cin b out b nc top view dhc package 16-lead (5mm s 3mm) plastic dfn b a c d t jmax = 125c, ja = 43c/w underside metal connected to v C (pcb connection optional) gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 out a Cin a +in a v + +in b Cin b out b nc out d Cin d +in d v C +in c Cin c out c nc b a c d t jmax = 150c, ja = 135c/w pin configuration
ltc6240/ltc6241/ltc6242 3 624012fe lead free finish tape and reel part marking* package description specified temperature range ltc6240cs5#pbf ltc6240cs5#trpbf ltcrr 5-lead plastic tsot-23 0c to 70c ltc6240hvcs5#pbf ltc6240hvcs5#trpbf ltcrs 5-lead plastic tsot-23 0c to 70c ltc6240is5#pbf ltc6240is5#trpbf ltcrr 5-lead plastic tsot-23 C40c to 85c ltc6240hvis5#pbf ltc6240hvis5 #trpbf ltcrs 5-lead plastic tsot-23 C40c to 85c ltc6240hs5#pbf ltc6240hs5#trpbf ltcrr 5-lead plastic tsot-23 C40c to 125c ltc6240hvhs5#pbf ltc6240hvhs5#trpbf ltcrs 5-lead plastic tsot-23 C40c to 125c ltc6240cs8#pbf ltc6240cs8#trpbf 6240 8-lead plastic so 0c to 70c ltc6240hvcs8#pbf ltc6240hvcs8#trpbf 6240hv 8-lead plastic so 0c to 70c ltc6240is8#pbf ltc6240is8#trpbf 6240i 8-lead plastic so C40c to 85c ltc6240hvis8#pbf ltc6240hvis8#trpbf 240hvi 8-lead plastic so C40c to 85c ltc6240hs8#pbf ltc6240hs8#trpbf 6240h 8-lead plastic so C40c to 125c ltc6240hvhs8#pbf ltc6240hvhs8#trpbf 240hvh 8-lead plastic so C40c to 125c ltc6241cdd#pbf ltc6241cdd#trpbf lbpd 8-lead (3mm 3mm) plastic dfn 0c to 70c ltc6241hvcdd#pbf ltc6241hvcdd#trpbf lbrr 8-lead (3mm 3mm) plastic dfn 0c to 70c ltc6241idd#pbf ltc6241idd#trpbf lbpd 8-lead (3mm 3mm) plastic dfn C40c to 85c ltc6241hvidd#pbf ltc6241hvidd#trpbf lbrr 8-lead (3mm 3mm) plastic dfn C40c to 85c ltc6241cs8#pbf ltc6241cs8#trpbf 6241 8-lead plastic so 0c to 70c ltc6241hvcs8#pbf ltc6241hvcs8#trpbf 6241hv 8-lead plastic so 0c to 70c ltc6241is8#pbf ltc6241is8#trpbf 6241i 8-lead plastic so C40c to 85c ltc6241hvis8#pbf ltc6241hvis8#trpbf 241hvi 8-lead plastic so C40c to 85c ltc6241hs8#pbf ltc6241hs8#trpbf 6241h 8-lead plastic so C40c to 125c ltc6241hvhs8#pbf ltc6241hvhs8#trpbf 241hvh 8-lead plastic so C40c to 125c ltc6242cdhc#pbf ltc6242cdhc#trpbf 6242 16-lead (5mm 3mm) plastic dfn 0c to 70c ltc6242hvcdhc#pbf ltc6242hvcdhc#trpbf 6242hv 16-lead (5mm 3mm) plastic dfn 0c to 70c ltc6242idhc#pbf ltc6242idhc#trpbf 6242 16-lead (5mm 3mm) plastic dfn C40c to 85c ltc6242hvidhc#pbf ltc6242hvidhc#trpbf 6242hv 16-lead (5mm 3mm) plastic dfn C40c to 85c ltc6242cgn#pbf ltc6242cgn#trpbf 6242 16-lead plastic ssop 0c to 70c ltc6242hvcgn#pbf ltc6242hvcgn#trpbf 6242hv 16-lead plastic ssop 0c to 70c ltc6242ign#pbf ltc6242ign#trpbf 6242i 16-lead plastic ssop C40c to 85c ltc6242hvign#pbf ltc6242hvign#trpbf 242hvi 16-lead plastic ssop C40c to 85c ltc6242hgn#pbf ltc6242hgn#trpbf 6242h 16-lead plastic ssop C40c to 125c ltc6242hvhgn#pbf ltc6242hvhgn#trpbf 242hvh 16-lead plastic ssop C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ order information
ltc6240/ltc6241/ltc6242 4 624012fe available options part number amps/package specified temp range specified supply voltage package part marking ltc6240cs5 1 0c to 70c 3v, 5v sot-23 ltcrr ltc6240cs8 1 0c to 70c 3v, 5v so-8 6240 ltc6240hvcs5 1 0c to 70c 3v, 5v, 5v sot-23 ltcrs ltc6240hvcs8 1 0c to 70c 3v, 5v, 5v so-8 6240hv ltc6240is5 1 C40c to 85c 3v, 5v sot-23 ltcrr ltc6240is8 1 C40c to 85c 3v, 5v so-8 6240i ltc6240hvis5 1 C40c to 85c 3v, 5v, 5v sot-23 ltcrs ltc6240hvis8 1 C40c to 85c 3v, 5v, 5v so-8 240hvi ltc6240hs5 1 C40c to 125c 3v, 5v sot-23 ltcrr ltc6240hs8 1 C40c to 125c 3v, 5v so-8 6240h ltc6240hvhs5 1 C40c to 125c 3v, 5v, 5v sot-23 ltcrs ltc6240hvhs8 1 C40c to 125c 3v, 5v, 5v so-8 240hvh ltc6241cs8 2 0c to 70c 3v, 5v so-8 6241 ltc6241cdd 2 0c to 70c 3v, 5v dd lbpd ltc6241hvcs8 2 0c to 70c 3v, 5v, 5v so-8 6241hv ltc6241hvcdd 2 0c to 70c 3v, 5v, 5v dd lbrr ltc6241is8 2 C40c to 85c 3v, 5v so-8 6241i ltc6241idd 2 C40c to 85c 3v, 5v dd lbpd ltc6241hvis8 2 C40c to 85c 3v, 5v, 5v so-8 241hvi ltc6241hvidd 2 C40c to 85c 3v, 5v, 5v dd lbrr ltc6241hs8 2 C40c to 125c 3v, 5v so-8 6241h ltc6241hvhs8 2 C40c to 125c 3v, 5v, 5v so-8 241hvh ltc6242cgn 4 0c to 70c 3v, 5v gn 6242 ltc6242cdhc 4 0c to 70c 3v, 5v dhc 6242 ltc6242hvcgn 4 0c to 70c 3v, 5v, 5v gn 6242hv ltc6242hvcdhc 4 0c to 70c 3v, 5v, 5v dhc 6242hv ltc6242ign 4 C40c to 85c 3v, 5v gn 6242i ltc6242idhc 4 C40c to 85c 3v, 5v dhc 6242 ltc6242hvign 4 C40c to 85c 3v, 5v, 5v gn 242hvi ltc6242hvidhc 4 C40c to 85c 3v, 5v, 5v dhc 6242hv ltc6242hgn 4 C40c to 125c 3v, 5v gn 6242h ltc6242hvhgn 4 C40c to 125c 3v, 5v, 5v gn 242hvh
ltc6240/ltc6241/ltc6242 5 624012fe electrical characteristics (ltc6240c/i, ltc6240hvc/i, ltc6241c/i, ltc6241hvc/i, ltc6242c/i, ltc6242hvc/i) the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v s = 5v, 0v, v cm = 2.5v unless otherwise noted. symbol parameter conditions min typ max units v os input offset voltage (note 4) ltc6241 s8 0c to 70c C40c to 85c l l 40 125 250 300 v v v ltc6242 gn 0c to 70c C40c to 85c l l 50 150 275 300 v v v ltc6240 0c to 70c C40c to 85c l l 50 175 300 350 v v v ltc6241 dd, ltc6242 dhc 0c to 70c C40c to 85c l l 100 550 650 725 v v v v os match channel-to-channel (note 5) ltc6241 s8 0c to 70c C40c to 85c l l 40 160 300 375 v v v ltc6242 gn 0c to 70c C40c to 85c l l 50 185 325 400 v v v ltc6241 dd, ltc6242 dhc 0c to 70c C40c to 85c l l 150 650 700 750 v v v tc v os input offset voltage drift (note 6) l 0.7 2.5 v/c i b input bias current (notes 4, 7) ltc6241, ltc6242 l 0.2 75 pa pa ltc6240 l 0.2 1 75 pa pa i os input offset current (notes 4, 7) ltc6241, ltc6242 l 0.2 75 pa pa ltc6240 l 0.2 1 75 pa pa input noise voltage 0.1hz to 10hz 550 nv p-p e n input noise voltage density f = 1khz 7 10 nv/ hz i n input noise current density (note 8) 0.56 fa/ hz r in input resistance common mode 10 12 c in input capacitance differential mode common mode f = 100khz 3.5 3 pf pf v cm input voltage range guaranteed by cmrr l 0 3.5 v cmrr common mode rejection 0v v cm 3.5v l 80 105 db cmrr match channel-to-channel (note 5) l 76 95 db
ltc6240/ltc6241/ltc6242 6 624012fe symbol parameter conditions min typ max units a vol large signal voltage gain v o = 1v to 4v r l = 10k to v s /2 0c to 70c C40c to 85c l l 425 300 200 1600 v/mv v/mv v/mv v o = 1.5v to 3.5v r l = 1k to v s /2 0c to 70c C40c to 85c l l 90 60 50 215 v/mv v/mv v/mv v ol output voltage swing low (note 9) no load i sink = 1ma i sink = 5ma l l l 7 40 190 30 75 325 mv mv mv v oh output voltage swing high (note 9) no load i source = 1ma i source = 5ma l l l 11 45 190 30 75 325 mv mv mv psrr power supply rejection v s = 2.8v to 6v, v cm = 0.2v l 80 104 db psrr match channel-to-channel (note 5) l 74 100 db minimum supply voltage (note 10) l 2.8 v i sc short-circuit current l 15 30 ma i s supply current per ampli? er ltc6241, ltc6242 0c to 70c C40c to 85c l l 1.8 2.2 2.3 2.4 ma ma ma ltc6240 0c to 70c C40c to 85c l l 2 2.4 2.5 2.6 ma ma ma gbw gain bandwidth product frequency = 20khz, r l = 1k l 13 18 mhz sr slew rate (note 11) a v = C2, r l = 1k l 5 10 v/s fpbw full power bandwidth (note 12) v out = 3v p-p , r l = 1k l 0.53 1.06 mhz t s settling time v step = 2v, a v = C1, r l = 1k, 0.1% 1100 ns electrical characteristics (ltc6240c/i, ltc6240hvc/i, ltc6241c/i, ltc6241hvc/i, ltc6242c/i, ltc6242hvc/i) the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v s = 5v, 0v, v cm = 2.5v unless otherwise noted.
ltc6240/ltc6241/ltc6242 7 624012fe electrical characteristics (ltc6240c/i, ltc6240hvc/i, ltc6241c/i, ltc6241hvc/i, ltc6242c/i, ltc6242hvc/i) the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v s = 3v, 0v, v cm = 1.5v unless otherwise noted. symbol parameter conditions min typ max units v os input offset voltage (note 4) ltc6241 s8 0c to 70c C40c to 85c l l 40 175 275 325 v v v ltc6242 gn 0c to 70c C40c to 85c l l 60 200 275 325 v v v ltc6240 0c to 70c C40c to 85c l l 50 200 325 375 v v v ltc6241 dd, ltc6242 dhc 0c to 70c C40c to 85c l l 100 550 650 725 v v v v os match channel-to-channel (note 5) ltc6241 s8 0c to 70c C40c to 85c l l 40 200 325 400 v v v ltc6242 gn 0c to 70c C40c to 85c l l 60 225 325 400 v v v ltc6241 dd, ltc6242 dhc 0c to 70c C40c to 85c l l 150 650 700 750 v v v tc v os input offset voltage drift (note 6) l 0.7 2.5 v/c i b input bias current (notes 4, 7) ltc6241, ltc6242 l 0.2 75 pa pa ltc6240 l 0.2 1 75 pa pa i os input offset current (notes 4, 7) ltc6241, ltc6242 l 0.2 75 pa pa ltc6240 l 0.2 1 75 pa pa v cm input voltage range guaranteed by cmrr l 0 1.5 v cmrr common mode rejection 0v v cm 1.5v l 78 100 db cmrr match channel-to-channel (note 5) l 76 95 db a vol large signal voltage gain v o = 1v to 2v r l = 10k to v s /2 0c to 70c C40c to 85c l l 140 100 75 600 v/mv v/mv v/mv v ol output voltage swing low (note 9) no load i sink = 1ma l l 3 65 30 110 mv mv v oh output voltage swing high (note 9) no load i source = 1ma l l 4 70 30 120 mv mv psrr power supply rejection v s = 2.8v to 6v, v cm = 0.2v l 80 104 db psrr match channel-to-channel (note 5) l 74 100 db minimum supply voltage (note 10) l 2.8 v i sc short-circuit current l 36 ma
ltc6240/ltc6241/ltc6242 8 624012fe symbol parameter conditions min typ max units v os input offset voltage (note 4) ltc6241 s8 0c to 70c C40c to 85c l l 50 175 275 325 v v v ltc6242 gn 0c to 70c C40c to 85c l l 60 200 275 325 v v v ltc6240 0c to 70c C40c to 85c l l 60 250 350 400 v v v ltc6241 dd, ltc6242 dhc 0c to 70c C40c to 85c l l 100 550 650 725 v v v v os match channel-to-channel (note 5) ltc6241 s8 0c to 70c C40c to 85c l l 50 200 325 400 v v v ltc6242 gn 0c to 70c C40c to 85c l l 60 225 325 400 v v v ltc6241 dd, ltc6242 dhc 0c to 70c C40c to 85c l l 150 650 700 750 v v v tc v os input offset voltage drift (note 6) l 0.7 2.5 v/c i b input bias current (notes 4, 7) ltc6241, ltc6242 l 0.5 75 pa pa ltc6240 l 0.5 1 75 pa pa i os input offset current (notes 4, 7) ltc6241, ltc6242 l 0.2 75 pa pa ltc6240 l 0.2 1 75 pa pa input noise voltage 0.1hz to 10hz 550 nv p-p (ltc6240hvc/i, ltc6241hvc/i, ltc6242hvc/i) the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v s = 5v, 0v, v cm = 0v unless otherwise noted. electrical characteristics (ltc6240c/i, ltc6240hvc/i, ltc6241c/i, ltc6241hvc/i, ltc6242c/i, ltc6242hvc/i) the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v s = 3v, 0v, v cm = 1.5v unless otherwise noted. symbol parameter conditions min typ max units i s supply current per ampli? er ltc6241, ltc6242 0c to 70c C40c to 85c l l 1.4 1.7 1.8 1.9 ma ma ma ltc6240 0c to 70c C40c to 85c l l 1.5 1.9 2 2.1 ma ma ma gbw gain bandwidth product frequency = 20khz, r l = 1k l 12 17 mhz
ltc6240/ltc6241/ltc6242 9 624012fe electrical characteristics (ltc6240hvc/i, ltc6241hvc/i, ltc6242hvc/i) the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v s = 5v, 0v, v cm = 0v unless otherwise noted. symbol parameter conditions min typ max units e n input noise voltage density f = 1khz 7 10 nv/ hz i n input noise current density (note 8) 0.56 fa/ hz r in input resistance common mode 10 12 c in input capacitance differential mode common mode f = 100khz 3.5 3 pf pf v cm input voltage range guaranteed by cmrr l C5 3.5 v cmrr common mode rejection C5v v cm 3.5v l 83 105 db cmrr match channel-to-channel (note 5) l 76 95 db a vol large signal voltage gain v o = C3.5v to 3.5v r l = 10k 0c to 70c C40c to 85c l l 775 600 500 2700 v/mv v/mv v/mv r l = 1k 0c to 70c C40c to 85c l l 150 90 75 360 v/mv v/mv v/mv v ol output voltage swing low (note 9) no load i sink = 1ma i sink = 10ma l l l 15 45 360 30 75 550 mv mv mv v oh output voltage swing high (note 9) no load i source = 1ma i source = 10ma l l l 15 45 360 30 75 550 mv mv mv psrr power supply rejection v s = 2.8v to 11v, v cm = 0.2v l 85 110 db psrr match channel-to-channel (note 5) l 82 106 db minimum supply voltage (note 10) l 2.8 v i sc short-circuit current l 15 35 ma i s supply current per ampli? er ltc6241, ltc6242 0c to 70c C40c to 85c l l 2.5 3.2 3.3 3.7 ma ma ma ltc6240 0c to 70c C40c to 85c l l 2.7 3.3 3.4 3.8 ma ma ma gbw gain bandwidth product frequency = 20khz, r l = 1k l 13 18 mhz sr slew rate (note 11) a v = C2, r l = 1k l 5.5 10 v/s fpbw full power bandwidth (note 12) v out = 3v p-p , r l = 1k l 0.58 1.06 mhz t s settling time v step = 2v, a v = C1, r l = 1k, 0.1% 900 ns
ltc6240/ltc6241/ltc6242 10 624012fe (ltc6240h/ltc6240hvh, ltc6241h/ltc6241hvh, ltc6242h/ltc6242hvh) the l denotes the speci? cations which apply from C40c to 125c, otherwise speci? cations are at t a = 25c. v s = 5v, 0v, v cm = 2.5v unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units v os input offset voltage (note 4) ltc6241 s8 l 40 125 400 v v ltc6242 gn l 50 150 400 v v ltc6240 l 50 175 450 v v v os match channel-to-channel (note 5) ltc6241 s8 l 40 160 400 v v ltc6242 gn l 50 185 400 v v tc v os input offset voltage drift (note 6) l 0.7 2.5 v/c i b input bias current (notes 4, 7) ltc6241, ltc6242 l 0.2 1.5 pa na ltc6240 l 0.2 1 2.5 pa na i os input offset current (notes 4, 7) ltc6241, ltc6242 l 0.2 150 pa pa ltc6240 l 0.2 1 750 pa pa v cm input voltage range guaranteed by cmrr l 0 3.5 v cmrr common mode rejection 0v v cm 3.5v l 78 db cmrr match channel-to-channel (note 5) l 74 db a vol large signal voltage gain v o = 1v to 4v r l = 10k to v s /2 l 425 200 1600 v/mv v/mv v o = 1.5v to 3.5v r l = 1k to v s /2 l 90 40 215 v/mv v/mv v ol output voltage swing low (note 9) no load i sink = 1ma i sink = 5ma l l l 30 85 325 mv mv mv v oh output voltage swing high (note 9) no load i source = 1ma i source = 5ma l l l 30 85 325 mv mv mv psrr power supply rejection v s = 2.8v to 6v, v cm = 0.2v l 78 db psrr match channel-to-channel (note 5) l 74 db minimum supply voltage (note 10) l 2.8 v i sc short-circuit current l 15 ma i s supply current per ampli? er ltc6241, ltc6242 l 1.8 2.2 2.4 ma ma ltc6240 l 2 2.4 2.8 ma ma gbw gain bandwidth product frequency = 20khz, r l = 1k l 12 mhz sr slew rate (note 11) a v = C2, r l = 1k l 4.5 v/s fpbw full power bandwidth (note 12) v out = 3v p-p , r l = 1k l 0.48 mhz
ltc6240/ltc6241/ltc6242 11 624012fe electrical characteristics (ltc6240h/ltc6240hvh, ltc6241h/ltc6241hvh, ltc6242h/ltc6242hvh) the l denotes the speci? cations which apply from C40c to 125c, otherwise speci? cations are at t a = 25c. v s = 3v, 0v, v cm = 1.5v unless otherwise noted. symbol parameter conditions min typ max units v os input offset voltage (note 4) ltc6241 s8 l 40 175 400 v v ltc6242 gn l 60 200 400 v v ltc6240 l 50 200 450 v v v os match channel-to-channel (note 5) ltc6241 s8 l 40 200 400 v v ltc6242 gn l 60 225 400 v v tc v os input offset voltage drift (note 6) l 0.7 2.5 v/c i b input bias current (notes 4, 7) ltc6241, ltc6242 l 0.2 1.5 pa na ltc6240 l 0.2 1 2.5 pa na i os input offset current (notes 4, 7) ltc6241, ltc6242 l 0.2 150 pa pa ltc6240 l 0.2 1 750 pa pa v cm input voltage range guaranteed by cmrr l 0 1.5 v cmrr common mode rejection 0v v cm 1.5v l 75 db cmrr match channel-to-channel (note 5) l 74 db a vol large signal voltage gain v o = 1v to 2v r l = 10k to v s /2 l 140 65 600 v/mv v/mv v ol output voltage swing low (note 9) no load i sink = 1ma l l 30 130 mv mv v oh output voltage swing high (note 9) no load i source = 1ma l l 30 130 mv mv psrr power supply rejection v s = 2.8v to 6v, v cm = 0.2v l 78 db psrr match channel-to-channel (note 5) l 74 db minimum supply voltage (note 10) l 2.8 v i sc short-circuit current l 2.5 ma i s supply current per ampli? er ltc6241, ltc6242 l 1.4 1.7 1.9 ma ma ltc6240 l 1.5 1.9 2.1 ma ma gbw gain bandwidth product frequency = 20khz, r l = 1k l 10 mhz
ltc6240/ltc6241/ltc6242 12 624012fe (ltc6240hvh/ltc6241hvh/ltc6242hvh) the l denotes the speci? cations which apply from C40c to 125c, otherwise speci? cations are at t a = 25c. v s = 5v, v cm = 0v unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units v os input offset voltage (note 4) ltc6241 s8 l 50 175 400 v v ltc6242 gn l 60 200 400 v v ltc6240 l 60 250 450 v v v os match channel-to-channel (note 5) ltc6241 s8 l 50 200 400 v v ltc6242 gn l 60 225 400 v v tc v os input offset voltage drift (note 6) l 0.7 2.5 v/c i b input bias current (notes 4, 7) ltc6241, ltc6242 l 0.5 1.5 pa na ltc6240 l 0.5 1 2.5 pa na i os input offset current (notes 4, 7) ltc6241, ltc6242 l 0.2 150 pa pa ltc6240 l 0.2 1 750 pa pa v cm input voltage range guaranteed by cmrr l C5 3.5 v cmrr common mode rejection C5v v cm 3.5v l 80 db cmrr match channel-to-channel (note 5) l 76 db a vol large signal voltage gain v o = C3.5v to 3.5v r l = 10k l 775 350 2700 v/mv v/mv r l = 1k l 150 60 360 v/mv v/mv v ol output voltage swing low (note 9) no load i sink = 1ma i sink = 10ma l l l 30 85 600 mv mv mv v oh output voltage swing high (note 9) no load i source = 1ma i source = 10ma l l l 30 85 600 mv mv mv psrr power supply rejection v s = 2.8v to 11v, v cm = 0.2v l 83 db psrr match channel-to-channel (note 5) l 82 db minimum supply voltage (note 10) l 2.8 v i sc short-circuit current l 15 ma i s supply current per ampli? er ltc6241, ltc6242 l 2.5 3.2 3.7 ma ma ltc6240 l 2.7 3.3 3.8 ma ma gbw gain bandwidth product frequency = 20khz, r l = 1k l 12 mhz sr slew rate (note 11) a v = C2, r l = 1k l 5 v/s fpbw full power bandwidth (note 12) v out = 3v p-p , r l = 1k l 0.53 mhz
ltc6240/ltc6241/ltc6242 13 624012fe note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: a heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted inde? nitely. note 3: the ltc6240c/ltc6240hvc/ltc6241c/ltc6241hvc, ltc6242c/ ltc6242hvc are guaranteed to meet speci? ed performance from 0c to 70c. they are designed, characterized and expected to meet speci? ed performance from C40c to 85c, but are not tested or qa sampled at these temperatures. the ltc6240i/ltc6240hvi, ltc6241i/ltc6241hvi, ltc6242i/ltc6242hvi are guaranteed to meet speci? ed performance from C40c to 85c. all versions of the ltc6240h/ltc6241h/ltc6242h are guaranteed to meet speci? ed performance from C40c to 125c. note 4: esd (electrostatic discharge) sensitive device. esd protection devices are used extensively internal to the ltc6240/ltc6241/ltc6242; however, high electrostatic discharge can damage or degrade the device. use proper esd handling precautions. note 5: matching parameters are the difference between the two ampli? ers a and d and between b and c of the ltc6242; between the two ampli? ers of the ltc6241. cmrr and psrr match are de? ned as follows: cmrr and psrr are measured in v/v on the matched ampli? ers. the difference is calculated between the matching sides in v/v. the result is converted to db. note 6: this parameter is not 100% tested. note 7: bias current at t a = 25c is 100% tested and guaranteed for the ltc6240 in the s8 package. the ltc6240s5, ltc6241 and ltc6242 are expected to achieve the same performance as the ltc6240s8. all parts are guaranteed to meet speci? cations over temperature. note 8: current noise is calculated from the formula: i n = (2qi b ) 1/2 where q = 1.6 10 C19 coulomb. the noise of source resistors up to 50g dominates the contribution of current noise. see also typical performance characteristics curve noise current vs frequency. note 9: output voltage swings are measured between the output and power supply rails. note 10: minimum supply voltage is guaranteed by the power supply rejection ratio test. note 11: slew rate is measured in a gain of C2 with r f = 1k and r g = 500. on the ltc6240/ltc6241/ltc6242, v s = 2.5v, v in is 1v and v out slew rate is measured between C1v and +1v. on the ltc6240hv/ ltc6241hv/ltc6242hv, v in is 2v and v out slew rate is measured between C2v and +2v. note 12: full-power bandwidth is calculated from the slew rate: fpbw = sr/v p-p . electrical characteristics
ltc6240/ltc6241/ltc6242 14 624012fe input bias current vs common mode voltage v os distribution ltc6241 v os distribution ltc6241 v os temperature coef? cient distribution ltc6241 supply current vs supply voltage offset voltage vs input common mode voltage input bias current vs common mode voltage v os temperature coef? cient distribution ltc6240 v os distribution ltc6240 typical performance characteristics input offset voltage (v) 0 number of units 10 30 40 50 90 6241 g01 20 60 70 80 C70 C50 C30 C10 70 30 50 10 v s = 2.5v so-8 package input offset voltage (v) 0 number of units 40 120 6241 g02 20 60 100 80 C350 C250 C150 C50 350 150 250 50 v s = 2.5v dd package distribution (v/c) 0 number of units 4 16 14 12 6241 g03 2 6 10 8 C1.0 C0.6 C0.2 0.2 1.8 1.0 1.4 0.6 v s = 2.5v 2 lots C55c to 125c input offset voltage (v) 0 percent of units 5 10 15 35 6241 g04 20 25 30 C70 C90 C110 C50 C30 C10 70 30 50 10 v s = 2.5v distribution (v/c) 0 number of units 2 6 8 10 18 6241 g05 4 12 14 16 C0.6 C0.2 1.8 1.4 1.0 0.6 0.2 v s = 5v, 0 v cm = 2.5v 2 lots C40c to 125c so-8 and sot23 packages total supply voltage (v) 0 2.0 2.5 3.0 610 6241 g06 1.5 1.0 24 812 0.5 0 supply current per amp (ma) 3.5 t a = C55c t a = 125c t a = 25c input common mode voltage (v) C0.5 offset voltage (v) 300 200 250 150 100 0 50 C50 C100 C150 C200 C250 C300 3.0 6241 g07 0 0.5 1.5 2.5 3.5 1.0 2.0 4.5 4.0 v s = 5v, 0v t a = C55c t a = 125c t a = 25c common mode voltage (v) 0 1.0 2.0 3.0 4.0 0.5 1.5 2.5 3.5 4.5 5.0 input bias current (pa) 1000 100 10 0.1 1 6241 g08 v s = 5v, 0v t a = 85c t a = 125c t a = 25c common mode voltage (v) C0.8 C0.6 C0.2 0.2 0.6 C0.4 0 0.4 0.8 1.0 input bias current (pa) 700 100 200 300 400 500 600 C400 C300 C200 C100 0 6241 g09 v s = 5v, 0v t a = 85c t a = 125c t a = 25c
ltc6240/ltc6241/ltc6242 15 624012fe output saturation voltage vs load current (output high) gain bandwidth and phase margin vs temperature open loop gain vs frequency input bias current vs temperature output saturation voltage vs load current (output low) gain bandwidth and phase margin vs supply voltage slew rate vs temperature common mode rejection ratio vs frequency output impedance vs frequency typical performance characteristics temperature (c) 25 45 65 85 105 35 55 75 95 115 125 input bias current (pa) 6241 g10 v cm = v s /2 v s = 5v v s = 10v 1000 100 10 0.1 1 load current (ma) 0.01 output low saturation voltage (v) 0.1 0.1 10 100 6241 g11 0.001 1 10 1 v s = 5v, 0v t a = 125c t a = C55c t a = 25c load current (ma) output high saturation voltage (v) 0.1 0.1 10 100 6241 g12 0.01 1 10 1 v s = 5v, 0v t a = 125c t a = C55c t a = 25c temperature (c) C55 C35 5 45 85 C15 25 65 105 125 gain bandwidth (mhz) phase margin (deg) 70 30 40 50 60 0 10 20 30 40 6241 g13 c l = 5pf r l = 1k phase margin gain bandwidth v s = 1.5v v s = 5v v s = 1.5v v s = 5v frequency (hz) 10k 100k 10m 1m 100m gain (db) phase (deg) C20 0 C10 10 20 30 40 50 60 70 80 C80 C40 C60 C20 0 20 40 60 80 100 120 6241 g14 c l = 5pf r l = 1k v cm = v s /2 phase gain v s = 1.5v v s = 5v v s = 1.5v v s = 5v total supply voltage (v) 048 2 6 10 12 gain bandwidth (mhz) phase margin (deg) 70 60 40 50 0 10 20 30 6241 g15 t a = 25c c l = 5pf r l = 1k phase margin gain bandwidth temperature (c) C55 C35 5 45 85 C15 25 65 105 125 slew rate (v/s) 4 6 8 10 12 14 16 18 20 6241 g16 a v = C2 r f = 1k, r g = 500 conditions: see note 12 v s = 5v rising v s = 5v falling v s = 2.5v falling v s = 2.5v rising frequency (hz) output impedance () 10k 1m 10m 6241 g17 100k t a = 25c v s = 2.5v a v = 10 a v = 1 0.01 10 10k 1 0.10 100 1k a v = 2 frequency (hz) 10k 100k 10m 1m 100m common mode rejection (db) C10 0 10 20 30 40 50 60 70 100 90 80 6241 g18 t a = 25c v s = 2.5v
ltc6240/ltc6241/ltc6242 16 624012fe input capacitance vs frequency minimum supply voltage output short-circuit current vs power supply voltage open loop gain open loop gain open loop gain channel separation vs frequency power supply rejection ratio vs frequency offset voltage vs output current typical performance characteristics power supply rejection ratio (db) 90 80 70 60 50 40 30 20 10 0 1k 100k 1m 100m 10k 10m frequency (hz) 6241 g20 t a = 25c v s = 2.5v positive supply negative supply frequency (hz) 10k 100k 10m 1m 100m voltage gain (db) C120 0 C10 C20 C30 C40 C50 C60 C70 C110 C100 C90 C80 6241 g19 t a = 25c v s = 2.5v a v = 1 input capacitance (pf) 16 14 12 10 8 6 4 2 0 1k 100k 1m 100m 10k 10m frequency (hz) 6241 g21 v s = 1.5v c cm total supply voltage (v) 02 6 14 8 37 5910 change in offset voltage (v) 100 20 40 60 80 C100 C80 C40 C60 C20 0 6241 g22 v cm = v s /2 t a = 125c t a = C55c t a = 25c power supply voltage (v) 1.5 2.5 4.5 2.0 3.5 3.0 4.0 5.0 output short-circuit current (ma) 50 10 20 30 40 C50 C40 C20 C30 C10 0 6241 g23 sourcing sinking t a = 125c t a = 125c t a = C55c t a = C55c t a = 25c output voltage (v) 0 0.5 2.5 1.5 1.0 2.0 3.0 input voltage (v) 120 100 20 40 60 80 0 6241 g24 t a = 25c v s = 3v, 0v r l = 100k r l = 10k output voltage (v) 012 5 34 input voltage (v) 120 100 20 40 60 80 C20 0 6241 g25 t a = 25c v s = 5v, 0v r l = 1k r l = 10k output voltage (v) C5 C4 0 C2 C3 C1 5 1234 input voltage (v) 100 20 40 60 80 C60 C40 C20 0 6241 g26 t a = 25c v s = 5v r l = 1k r l = 10k output current (ma) C50 C40 C30 C20 C10 10 30 20 04050 offset voltage (v) 500 400 100 200 300 C500 C400 C300 C100 C200 0 6241 g27 t a = 125c t a = C55c t a = 25c v s = 5v
ltc6240/ltc6241/ltc6242 17 624012fe warm-up drift vs time noise voltage vs frequency series output resistance and overshoot vs capacitive load series output resistance and overshoot vs capacitive load 0.1hz to 10hz voltage noise noise current vs frequency minimum output series resistance vs capacitive load settling time vs output step (inverting) settling time vs output step (non-inverting) typical performance characteristics time after power up (s) 010 30 20 54060 50 15 35 25 45 55 change in offset voltage (v) 25 15 20 C5 0 10 5 6241 g28 t a = 25c v s = 1.5v v s = 2.5v v s = 5v frequency (hz) 20 10 noise voltage (nv/ hz ) 30 40 50 60 1 100 1k 100k 6241 g29 0 10 10k t a = 25c v s = 2.5v v cm = 0v time (1s/div) voltage noise (200nv/div) 6241 g30 v s = 5v, 0v frequency (hz) 1 noise current (fa/ hz ) 10 100 10k 100k 6241 g31 0.1 1k 1000 100 t a = 25c v s = 2.5v v cm = 0v capacitive load (pf) 10 overshoot (%) 60 50 40 30 20 10 0 100 1000 6241 g32 r s = 50 r s = 10 v s = 2.5v a v = C1 r s 1k 1k c l 75pf + C 0.01f 1f 0.1f 1000pf 100pf capacitive load 1 output series resistance () 10 10pf 10f 6241 g33 0.1 1000 100 v s = 2.5v <30% overshoot capacitive load (pf) 10 overshoot (%) 60 50 40 30 20 10 0 100 1000 6241 g34 r s = 50 r s = 10 v s = 2.5v a v = C2 r s 500 1k c l 75pf + C output step (v) C4 C2 3 C3 1 0 C1 2 4 settling time (s) 3.5 1.5 2.0 2.5 3.0 0 0.5 1.0 6241 g35 10mv 1mv 10mv 1mv t a = 25c v s = 5v a v = 1 v out v in 1k + C 3.0 1.5 2.0 2.5 0 0.5 1.0 output step (v) C4 C2 3 C3 1 0 C1 2 4 settling time (s) 6241 g36 10mv 1mv 10mv 1mv t a = 25c v s = 5v a v = C1 v out v in 1k + C 1k 1k
ltc6240/ltc6241/ltc6242 18 624012fe distortion vs frequency distortion vs frequency maximum undistorted output signal vs frequency distortion vs frequency large signal response large signal response output overdrive recovery small signal response distortion vs frequency typical performance characteristics frequency (hz) 10k 100k 1m 10m output voltage swinging (v p-p ) 10 7 4 1 8 5 2 9 6 3 6241 g37 t a = 25c v s = 5v hd 2 , hd 3 < C40dbc a v = +2 a v = C1 frequency (hz) 10k 100k 1m 10m distortion (dbc) C30 C60 C90 C100 C50 C80 C40 C70 6241 g38 v s = 2.5v a v = 1 v out = 2v p-p r l = 1k, 2nd r l = 1k, 3rd frequency (hz) 10k 100k 1m 10m distortion (dbc) C30 C60 C90 C100 C50 C80 C40 C70 6241 g39 v s = 5v a v = 1 v out = 2v p-p r l = 1k, 2nd r l = 1k, 3rd frequency (hz) 10k 100k 1m 10m distortion (dbc) C30 C60 C90 C100 C50 C80 C40 C70 6241 g40 v s = 2.5v a v = 2 v out = 2v p-p r l = 1k, 2nd r l = 1k, 3rd frequency (hz) 10k 100k 1m 10m distortion (dbc) C30 C60 C90 C100 C50 C80 C40 C70 6241 g41 v s = 5v a v = 2 v out = 2v p-p r l = 1k, 2nd r l = 1k, 3rd v s = 2.5v a v = 1 r l = 6241 g42 0v v s = 5v a v = 1 r l = 6241 g43 0v v s = 2.5v a v = C1 r l = 1k 6241 g44 0v v s = 2.5v a v = 3 r l = 500ns/div 6241 g45 0v 0v v in (1v/div) v out (2v/div)
ltc6240/ltc6241/ltc6242 19 624012fe ampli? er characteristics figure 1 is a simpli? ed schematic of the ampli? er, which has a pair of low noise input transistors m1 and m2. a simple folded cascode q1, q2 and r1, r2 allow the input stage to swing to the negative rail, while performing level shift to the differential drive generator. low offset voltage is accomplished by laser trimming the input stage. capacitor c1 reduces the unity cross frequency and im- proves the frequency stability without degrading the gain bandwidth of the ampli? er. capacitor cm sets the overall ampli? er gain bandwidth. the differential drive generator supplies signals to transistors m3 and m4 that swing the output from rail-to-rail. the photo of figure 2 shows the output response to an input overdrive with the ampli? er connected as a voltage follower. if the negative going input signal is less than a diode drop below v C , no phase inversion occurs. for input signals greater than a diode drop below v C , limit the current to 3ma with a series resistor r s to avoid phase inversion. esd the ltc6240/ltc6241/ltc6242 have reverse-biased esd protection diodes on all input and outputs as shown in figure 1. if these pins are forced beyond either supply, unlimited current will ? ow through these diodes. if the current is transient and limited to one hundred milliamps or less, no damage to the device will occur. the ampli? er input bias current is the leakage current of these esd diodes. this leakage is a function of the tempera- ture and common mode voltage of the ampli? er, as shown in the typical performance characteristics curves. noise the ltc6240/ltc6241/ltc6242 exhibit exceptionally low 1/f noise in the 0.1hz to 10hz region. this 550nv p-p noise allows these op amps to be used in a wide variety of high impedance low frequency applications, where zero-drift ampli? ers might be inappropriate due to their charge injection. in the frequency region above 1khz the ltc6240/ltc6241/ ltc6242 also show good noise voltage performance. in this frequency region, noise can easily be dominated by the total source resistance of the particular application. speci? cally, these ampli? ers exhibit the noise of a 3.1k resistor, meaning it is desirable to keep the source and feedback resistance at or below this value, i.e. r s + r g ||r fb 3.1k. above this total source impedance, the noise voltage is not dominated by the ampli? er. noise current can be estimated from the expression i n = 2qi b , where q = 1.6 ? 10 C19 coulombs. equating 4ktr f and r 2qi b f shows that for source resistors below 50g the ampli? er noise is dominated by the source resistance. see the typical performance characteristics curve noise current vs frequency. figure 1. simpli? ed schematic figure 2. unity gain follower test circuit applications information r2 q2 6241 f01 v in + i tail v in C v o v + v + v C v C v C cm desd5 differential drive generator bias desd6 v + desd2 v + desd4 v C desd1 v C desd3 r1 q1 m2 m1 m3 m4 c1 clamp +2.5v C2.5v 6241 f02 C + ltc6240 r s v in v out v out and v in of follower with large input overdrive v dd = +2.5v v ss = C2.5v
ltc6240/ltc6241/ltc6242 20 624012fe proprietary design techniques are used to obtain simulta- neous low 1/f noise and low input capacitance. low input capacitance is important when the ampli? er is used with high value source and feedback resistors. high frequency noise from the ampli? er tail current source, i tail in fig- ure 1, couples through the input capacitance and appears across these large source and feedback resistors. as an example, the photodiode ampli? er of figure 15 on the last page of this data sheet shows the noise results from the ltc6241 and the results of a competitive cmos ampli? er. the ltc6241 output is the ideal noise of a 1m resistor at room temperature, 130nv hz . half the noise the circuit shown in figure 3 can be used to achieve even lower noise voltage. by paralleling 4 ampli? ers the noise voltage can be lowered by 4 , or half as much noise. the C comes about from an rms summing of uncorrelated noise sources. this circuit maintains extremely high input resistance, and has a 250 output resistance. for lower output resistance, a buffer ampli? er can be added without in? uencing the noise. stability the good noise performance of these op amps can be at- tributed to large input devices in the differential pair. above several hundred kilohertz, the input capacitance rises and can cause ampli? er stability problems if left unchecked. when the feedback around the op amp is resistive (r f ), a pole will be created with r f , the source resistance, source capacitance (r s , c s ), and the ampli? er input capacitance. in low gain con? gurations and with r f and r s in even the kilohm range (figure 4), this pole can create excess phase shift and possibly oscillation. a small capacitor c f in parallel with r f eliminates this problem. low noise single-ended input to differential output ampli? er the circuit on the ? rst page of the data sheet is a low noise single-ended input to differential output ampli? er, with a 200k input impedance. the very low input bias current of the ltc6241 allows for these large input and feedback resistors. the 200k resistors, r1 and r2, along with c1 and c2 set the C3db bandwidth to 80khz. capacitor c3 is used to cancel effects of input capacitance, while c4 adds phase lead to compensate the phase lag of the second ampli? er. figure 3. parallel ampli? er lowers noise by 2x figure 4. compensating input capacitance applications information 10 6241 f03 C + 1/4 ltc6242 1k 1k 10 C + 1/4 ltc6242 1k 1k 10 C + 1/4 ltc6242 1k 1k 10 C + 1/4 ltc6242 1k 1k +2.5 C2.5 v in v o + C c in c s 6241 f04 r f r s output c f
ltc6240/ltc6241/ltc6242 21 624012fe the op amps good input offset voltage match and low input bias current means that the typical differential output offset voltage is less than 40v. a noise spectrum plot of the differential output is shown in figure 5. the guard ring should extend as far as necessary to shield the high impedance signal from any and all leakage paths. figure 6 shows the use of a guard ring on the ltc6241 in a unity gain con? guration. in this case the guard ring is connected to the output and is shielding the high impedance noninverting input from v C . figure 7 shows the inverting gain con? guration. a digitally programmable ac difference ampli? er the ltc6241 con? gured as a difference ampli? er, can be combined with a programmable gain ampli? er (pga) to obtain a low noise high speed programmable difference ampli? er. figure 8 shows the ltc6241 based as a single- supply ac ampli? er. one ltc6241 op amp is used at the circuits input as a standard four resistor difference ampli? er. figure 5. differential output noise achieving low input bias current the dd package is leadless and makes contact to the pcb beneath the package. solder ? ux used during the attach- ment of the part to the pcb can create leakage current paths and can degrade the input bias current performance of the part. all inputs are susceptible because the backside paddle is connected to v C internally. as the input voltage changes or if v C changes, a leakage path can be formed and alter the observed input bias current. for lowest bias current, use the ltc6240/ltc6241 in the so-8 and provide a guard ring around the inputs that are tied to a potential near the input voltage. layout considerations and a pcb guard ring in high source impedance applications such as ph probes, photodiodes, strain gauges, et cetera, the low input bias current of these parts requires a clean board layout to minimize additional leakage current into a high impedance signal node. a mere 100g of pc board resistance between a 5v supply trace and an input trace adds 50pa of leakage current, far greater then the input bias current of the operational ampli? er. a guard ring around the high impedance input traces driven by a low impedance source equal to the input voltage prevents such leakage problems. figure 6. sample layout. unity gain con? guration, using guard ring to shield high impedance input from board leakage figure 7. sample layout. inverting gain con? guration, using guard ring to shield high impedance input from board leakage applications information frequency (khz) 020 60 10 40 80 30 70 50 90 100 differential output voltage density (nv/ hz ) 140 60 80 100 120 0 20 40 6241 f05 v s = 2.5v t a = 25c C3db bw = 80khz ltc6241 s8 r out + in C in + v C leakage current no leakage current guard ring no solder mask over the guard ring ltc6241 f06 ltc6241 s8 ltc6241 f07 r r out + in C in + v C v in gnd
ltc6240/ltc6241/ltc6242 22 624012fe figure 8. wideband difference ampli? er with high input impedance and digitally programmable gain the low bias current and current noise of the ltc6241 allow the use of high valued input resistors, 100k or greater. resistors r1, r2, r3 and r4 are equal and the gain of the difference ampli? er is one. an ltc6910-2 pga ampli? es the difference ampli? er output with inverting gains of C1, C2, C4, C8, C16, C32 and C64. the second ltc6241 op amp is used as an integrator to set the dc output voltage equal to the lt6650 reference voltage v ref . the integrator drives the pga analog ground to provide a feedback loop, in addition to blocking any dc voltage through the pga. the reference voltage of the lt6650 can be set to a voltage from 400mv to v + C 350mv with resistors r5 and r6. if r6 is 20k or less, the error due to the lt6650 op amp bias current is negligible. the low voltage offset and drift of the ltc6241 integrator will not contribute any signi? cant error to the lt6650 reference voltage. the lt6650 v ref voltage has a maximum error of 2% with 1% resistors. the upper C3db frequency of the ampli? er is set by resistor r3 and capacitor c1 and is limited by the bandwidth of the pga when operated at a gain of 64. capacitor c2 is equal to c1 and is added to maintain good common mode rejection at high frequency. the lower C3db frequency is set by the integrator resistor r7, capacitor c3, and the gain setting of the ltc6910-2 pga. this lower C3db zero frequency is multiplied by the pga gain. the rail-to-rail output of the ltc6910-2 pga allows for a maximum output peak-to-peak voltage equal to twice the v ref voltage. at the maximum gain setting of 64, the maximum peak-to-peak difference between inputs v1 and v2 is equal to twice v ref divided by 64. example design: design a programmable gain ac differ- ence ampli? er, with a bandwidth of at least 10hz to 100khz, an input impedance equal to or greater than 100k, and an output dc reference equal to 1v. a. select input resistors r1, r2, r3 and r4 equal to 100k. b. if the upper C3db frequency is 100khz then c1 = 1/(2 ? r2 ? f3db) = 1/(6.28 ? 100k ? 100khz) = 15pf (to the nearest 5% value) and c2 = c1 = 15pf. c. select r7 equal to one 1m and set the lower C3db frequency to 10hz at the highest pga gain of 64, then c3 = gain/(2 ? r7 ? f3db) = 64/(6.28 ? 100k ? 10hz) = 1f. lower gains settings will give a lower f3db. d. calculate the value of r5 to set the lt6650 reference equal to 1v; v ref = 0.4(r5/r6 + 1), so r5 = r6(2.5v ref C 1). for r6 = 20k, r5 = 30k with v ref = 1v the maximum input difference voltage is equal to 2v/64 = 31.2mv. 40nvpp noise, 0.05v/c drift, chopped fet ampli? er figure 9s circuit combines the 5v rail-to-rail performance of the ltc6241hv with a pair of extremely low noise jfets con? gured in a chopper based carrier modulation scheme applications information 6241 f08 r4 r3 r2 C + 1/2 ltc6241 c1 c2 1f 0.1f 8 765 g2 g1 g0 1 1 2 234 agnd out in v C v + 0.1f v + v + r1 r1 = r2 = r3 = r4 v2 v1 r5 1k 1000pf 3 4 5 r6 20k ltc6910-2 lt6650 v out v ref C + 1/2 ltc6241 c3 r7 100 1f digital inputs g1 g2 go gain 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 C1 C2 C4 C8 C16 C32 C64 v out = (v1 C v2) gain + v ref v r r rkv ref ref =+ | ? = = 04 5 6 1 510 5 2 r620 .? ?? C k d bandwidth f f f rc high low high CC ?? ? 3 1 23 = = p 1273 f gain rc low = ?? ? p
ltc6240/ltc6241/ltc6242 23 624012fe figure 9. ultralow noise chopper ampli? er to achieve an extraordinarily low noise and low dc drift. the performance of this circuit is suited for the demand- ing transducer signal conditioning situations such as high resolution scales and magnetic search coils. the ltc1799s output is divided down to form a 2-phase 925hz square wave clock. this frequency, harmonically unrelated to 60hz, provides excellent immunity to harmonic beating or mixing effects which could cause instabilities. s1 and s2 receive complementary drive, causing a1 to see a chopped version of the input voltage. a1s square wave output is synchronously demodulated by s3 and s4. because these switches are synchronously driven with the input chopper, proper amplitude and polarity information is presented to a2, the dc output ampli? er. this stage integrates the square wave into a dc voltage, providing the output. the output is divided down (r2 and r1) and fed back to the input chopper where it serves as a zero signal reference. gain, in this case 1000, is set by the r1-r2 ratio. because a1 is ac coupled, its dc offset and drift do not affect the overall circuit offset, resulting in the extremely low offset and drift noted. the jfets have an input rc damper that minimizes offset voltage contribution due to parasitic switch behavior, resulting in the 1v offset speci? cation. applications information + C + C bias 10m 1f 14 15 16 3 2 1 s4 s3 240k 1f output a2 ltc6241hv a1 ltc6241hv 1f input 10k 8 7 11 s1 s2 9 6 10 r2 10k r1 10 noise offset drift open-loop gain i = 40nv p-p 0.1hz to 10hz = 1v = 0.05v/c r2 10 = 10 = 500pa +1 gain = 9 0.01f ?1 ?1 ?2 ?2 6241 f09 = 0.1% metal film resistor = 1% metal film resistor * ** = ltc201 quad = lsk389 = linear integrated systems fremont, ca 1f div r set ltc1799 v + 74c90 10 18.5khz out 74c74 2 to ?1 points to ?2 points q q 54.2k* to ltc201 v + pin 5v 5v C5v 5v 5v 925hz to ltc201 v C pin 1f 898** 5v C5v 898** lsk389 30.1 499** + +
ltc6240/ltc6241/ltc6242 24 624012fe by the sensor is forced across the feedback capacitor by the op amp action. because the feedback capacitor is 100 times smaller than the sensor, it will be forced to 100 times what would have been the sensors open circuit voltage. so the circuit gain is 100. the bene? t of this ap- proach is that the signal gain of the circuit is independent of any cable capacitance introduced between the sensor and the ampli? er. hence this circuit is favored for remote accelerometers where the cable length may vary. dif? culties with the circuit are inaccuracy of the gain setting with the small capacitor, and low frequency cutoff due to the bias resistor working into the small feedback capacitor. figure 12 shows a noninverting ampli? er approach. this approach has many advantages. first of all, the gain is set accurately with resistors rather than with a small capaci- tor. second, the low frequency cutoff is dictated by the bias resistor working into the large 770pf sensor, rather than into a small feedback capacitor, for lower frequency response. third, the noninverting topology can be paral- leled and summed (as shown) for scalable reductions in voltage noise. the only drawback to this circuit is that the parasitic capacitance at the input reduces the gain slightly. this circuit is favored in cases where parasitic input capacitances such as traces and cables will be relatively small and invariant. the noise measured over a 50 second interval, in figure 10, is 40nv in a 0.1hz to 10hz bandwidth.this low noise is at- tributed to the input jfets die size and current density. figure 11. classical inverting charge ampli? er figure 12. low noise noninverting shock sensor ampli? er figure 10. noise in a 0.1hz to 10hz bandwidth low noise shock sensor ampli? ers figures 11 and 12 show the ampli? ers realizing two dif- ferent approaches to amplifying signals from a capacitive sensor. the sensor in both cases is a 770pf piezoelectric shock sensor accelerometer, which generates charge under physical acceleration. figure 11 shows the classical charge ampli? er approach. the ltc6240 is in the inverting con? guration so the sensor looks into a virtual ground. all of the charge generated applications information 5s/div 6241 f10 20nv/div bias resistor vishay-techno crhv2512af1007g (or equivalent) main gain-setting element is a capacitor shock sensor murata-erie pkgs-00ld 770pf cable has unknown c r f 1g 6241 f11 v out = 110mv/g C + ltc6240 c f 7.7pf bias resistor vishay-techno crhv2512af1007g (or equivalent) 1g v s + 6241 f12 10k 1k 1k 100 v out = 110mv/g v s = 1.4v to 5.5v bw = 0.2hz to 10khz v out C + 1/2 ltc6241hv v s C 10k 100 C + 1/2 ltc6241hv shock sensor murata-erie pkgs-00ld 770pf
ltc6240/ltc6241/ltc6242 25 624012fe 1m transimpedance ampli? er with 43nv/hz output noise in a normal 1m transimpedance ampli? er, like that shown on the back page of this data sheet, the output noise density must be at least 130nv/ hz at room temperature. this is true even should the op amp be perfectly noiseless, because the 1m resistor provides 130nv/ hz of voltage noise at room temperature independently of the op amp. the circuit of figure 13 provides an overall transimpedance gain of 1m, but it has an output noise density of only 43nv/ hz , about 1/3 of the normal transimpedance ampli- ? er. it does this by taking a higher initial transimpedance gain of 10m and then attenuating by a factor of 10. the transistor section provides voltage gain and works on a 54v supply voltage to guarantee adequate output swing. by achieving an output swing of 50v before attenuation, the circuit provides an output swing to 5v after attenu- ation. the 10m resistor sets the gain of the tia stage and has a noise density of 400nv/ hz . after attenuation, the effective tia gain drops to 1m while the noise ? oor drops to 40nv/ hz , which clearly dominates the observed 43nv/ hz . note the additional bene? t that the offset voltage of the op amp is divided by 10. worst-case output offset for this circuit is 150v over temperature. reference buffer figure 14 shows the ltc6240 being utilized as a buffer in conjunction with the lt1019 reference. the passive r-c ? lter attenuates the reference noise and the ltc6240 provides a low noise buffer, resulting in an output noise of 8nv/ hz . figure 13. 1m transimpedance ampli? er with 43nv/ hz output noise figure 14. low noise reference buffer applications information 5v 54v C5v C1.5v 3pf photodiode 6241 f13 C5v 10k C + ltc6240hv 100pf 10m 1% 0.3pf 1k 10k 2.4k 33k mpsa06 43k 9.09k 1% 1/4w 1k 1% v out 1m gain (1v/a) 10m gain (10v/a) mpsa06 5v C5v 6241 f14 0.2 C + ltc6240hv 1m 10f ceramic or film 8nv/ hz v out 1f lt1019-2.5 180nv/ hz
ltc6240/ltc6241/ltc6242 26 624012fe dd package 8-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698) package description 3.00 p 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package 0.40 p 0.10 bottom viewexposed pad 1.65 p 0.10 (2 sides) 0.75 p 0.05 r = 0.125 typ 2.38 p 0.10 1 4 8 5 pin 1 top mark (note 6) 0.200 ref 0.00 C 0.05 (dd8) dfn 0509 rev c 0.25 p 0.05 2.38 p 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 1.65 p 0.05 (2 sides) 2.10 p 0.05 0.50 bsc 0.70 p 0.05 3.5 p 0.05 package outline 0.25 p 0.05 0.50 bsc
ltc6240/ltc6241/ltc6242 27 624012fe dhc package 16-lead plastic dfn (5mm 3mm) (reference ltc dwg # 05-08-1706) package description 3.00 0.10 (2 sides) 5.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wjed-1) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?xposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.20 typ 4.40 0.10 (2 sides) 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 ?0.05 (dhc16) dfn 1103 0.25 0.05 pin 1 notch 0.50 bsc 4.40 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.20 0.05 0.50 bsc 0.65 0.05 3.50 0.05 package outline 0.25 0.05
ltc6240/ltc6241/ltc6242 28 624012fe package description gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 15 14 13 .189 ?.196* (4.801 ?4.978) 12 11 10 9 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .007 ?.0098 (0.178 ?0.249) .0532 ?.0688 (1.35 ?1.75) .008 ?.012 (0.203 ?0.305) typ .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ?.165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale
ltc6240/ltc6241/ltc6242 29 624012fe s5 package 5-lead plastic tsot-23 (reference ltc dwg # 05-08-1635 rev b) 1.50 ?1.75 (note 4) 2.80 bsc 0.30 ?0.45 typ 5 plcs (note 3) datum ? 0.09 ?0.20 (note 3) s5 tsot-23 0302 rev b pin one 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 ?0.90 1.00 max 0.01 ?0.10 0.20 bsc 0.30 ?0.50 ref note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref package description
ltc6240/ltc6241/ltc6242 30 624012fe s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) package description .016 ?.050 (0.406 ?1.270) .010 ?.020 (0.254 ?0.508) 45 0 ?8 typ .008 ?.010 (0.203 ?0.254) so8 0303 .053 ?.069 (1.346 ?1.752) .014 ?.019 (0.355 ?0.483) typ .004 ?.010 (0.101 ?0.254) .050 (1.270) bsc 1 2 3 4 .150 ?.157 (3.810 ?3.988) note 3 8 7 6 5 .189 ?.197 (4.801 ?5.004) note 3 .228 ?.244 (5.791 ?6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm)
ltc6240/ltc6241/ltc6242 31 624012fe information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number e 07/10 update to simpli? ed schematic (figure 1) 19 (revision history begins at rev e)
ltc6240/ltc6241/ltc6242 32 624012fe linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt 0710 rev e ? printed in usa part number description comments ltc1151 15v zero-drift op amp dual high voltage operation 18v lt1792 low noise precision jfet op amp 6nv/ hz noise, 15v operation ltc2050 zero-drift op amp 2.7 volt operation, sot-23 ltc2051/ltc2052 dual/quad zero-drift op amp dual/quad version of ltc2050 in ms8/gn16 packages ltc2054/ltc2055 single/dual zero-drift op amp micropower version of the ltc2050/ltc2051 in sot-23 and dd packages ltc6244 dual 50mhz rail-to-rail op amp 100v v os(max) , 1pa i bias , 40v/v, slew rate figure 15. ultralow noise 1m 150khz photodiode ampli? er ltc6241 output noise spectrum. 1m resistor noise dominates; ideal performance competition output noise spectrum. op amp noise dominates; performance compromised related parts typical application r2 1.69k c3 180pf c1 1500pf +1.5v C1.5v C1.5v sfh213fa or equivalent (4pf) 6241 ta02a r f 1m r1 866 C + 1/2 ltc6241 C + 1/2 ltc6241 c2 1500pf c f 1pf 1m tia 150khz 3rd order butterworth filter r3 2k 1khz 101khz 10khz/div 6241 ta02b 0v 30nv/ hz per div 1khz 101khz 6241 ta02c 10khz/div 0v 30nv/ hz per div

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